RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design

suker004 · 发表于 2020-1-15 15:47:38

Thanks

napoleonlijun · 发表于 2020-1-16 00:19:52

thanks for sharing

buildgates · 发表于 2020-1-23 15:01:05

多谢分享。

pollaris · 发表于 2020-2-6 09:19:38

Than you!
Very useful

abutter · 发表于 2020-2-6 12:16:57

多谢分享

xd_laoxie · 发表于 2020-2-11 23:03:07

感谢分享！

IvanKao · 发表于 2020-2-12 16:02:49

Good book to study.
Thanks,

gellmann · 发表于 2020-2-12 22:05:10

不错的资料

maassmama · 发表于 2020-2-19 18:18:05

look good

qwpsmile · 发表于 2020-2-20 08:52:18

好书！！！

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[资料] RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design