Digital Logic Design Using Verilog: Coding and RTL Synthesis

gellmann · 发表于 2018-11-29 22:38:56

回复 1# Jason.tschen

谢谢分享，基础书籍

nick_liu · 发表于 2018-12-24 14:50:32

回复 1# Jason.tschen

good resourse

scrainwyf · 发表于 2018-12-26 09:41:13

thanks

k383556 · 发表于 2019-1-4 14:13:57

回复 1# Jason.tschen

thnx!

鲨鱼辣椒123 · 发表于 2019-1-5 11:41:05

不错，thx

nasirkhanpak25 · 发表于 2019-1-11 13:20:22

thanks u very much thanks a lot

nasirkhanpak25 · 发表于 2019-1-11 13:21:24

thanks u very much thanks a lot

nasirkhanpak25 · 发表于 2019-1-11 13:22:05

thanks u very much thanks a lot

nasirkhanpak25 · 发表于 2019-1-11 13:22:43

thanks u very much thanks a lot

rrww · 发表于 2019-1-13 08:48:07

r ttttret tret3ttre

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[原创] Digital Logic Design Using Verilog: Coding and RTL Synthesis