open source SystemVerilog verification IPs, models vip

ID2007 · 发表于 2020-11-16 09:16:06

After downloading and unpacking package you will have the following folder hierarchy:
• i2c_vip
• docs
• examples
• sim
• testbench
• verification_ip
• master
• slave
The Verification IP is located in the verification_ip folder. Just copy the content of this folder to
somewhere in your verification environment.

qq1014182606 · 发表于 2020-9-11 09:47:33

下載參考看看

b9803222 · 发表于 2020-9-9 22:32:06

謝謝

gyong22 · 发表于 2019-5-26 17:25:13

good materials.

prabakaran_123 · 发表于 2018-5-31 13:54:36

Thanks for all these verification IP's

gengbao · 发表于 2018-5-2 20:24:32

顶顶顶顶顶顶

huatiantian · 发表于 2018-3-25 21:30:33

great, thanks

chaozhanghu · 发表于 2017-11-1 19:45:31

非常不错

babikambing · 发表于 2017-10-31 23:18:56

回复 1# xiantongma

thanks for sharing

luyuan_0922 · 发表于 2017-10-30 09:36:01

这个猛啊！！！！

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[资料] open source SystemVerilog verification IPs, models vip