SPI同步总线接口的VHDL／Verilog代码实现，强力推荐

robber666 · 发表于 2011-9-9 11:56:26

have a look

ID2007 · 发表于 2011-10-30 12:02:51

The VSPI core implements an SPI interface compatible with the many
serial EEPROMs, and microcontrollers. The VSPI core is typically used
as an SPI master, but it can be configured as an SPI slave as well.

The SPI bus is a 3 wire bus that in effect links a serial shift
register between the "master" and the "slave". Typically both the
master and slave have an 8 bit shift register so the combined
register is 16 bits. When an SPI transfer takes place, the master and
slave shift their shift registers 8 bits and thus exchange their 8
bit register values.

liuxuejielxj · 发表于 2011-11-1 11:20:24

灰常感谢！

denap · 发表于 2011-11-13 10:53:09

Thanks！

418478935 · 发表于 2011-11-16 11:40:58

最近看这个看的头都大了

晕那

fort2121 · 发表于 2011-12-13 11:15:32

Thanks

drwang119 · 发表于 2011-12-19 22:37:22

xiexiefenxiang

lazioprocn · 发表于 2011-12-28 22:18:06

谢谢！

anonymous_es · 发表于 2011-12-30 15:02:01

多谢分享

memo07 · 发表于 2012-1-6 00:53:19

参考一下【]

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[资料] SPI同步总线接口的VHDL／Verilog代码实现，强力推荐

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