/opt/synp/vcs/T-2022.06-SP1/doc/examples/basic-hdl/verilog/syn_fifo$ make
\rm -rf simv* csrc* *.log
vcs fifo.v tb_fifo.v +v2k -debug_access+pp+f -l comp.log
Sorry, Linux version 6.8.0-60-generic is not supported
For assistance, please contact technical support
at vcs_support@synopsys.com or call 1-800-VERILOG
make: *** [Makefile:7:comp] 错误 1