ADE L仿真问题

Ecooq

Maximum value achieved for any signal of each quantity:
V: V(TEST_CESHI_kaiguan.A[8]) = 19 V
I: I(TEST_CESHI_kaiguan.V16:p) = 186.7 uA
Maximum value of each quantity, excluding Verilog-A modules and dangling current sources:
V: V(TEST_CESHI_kaiguan.AVDD) = 18 V
I: I(TEST_CESHI_kaiguan.V16:p) = 186.7 uA
Convergence achieved in 148 iterations.
DC simulation time: CPU = 1.17198 s, elapsed = 1.17483 s.
Total time required for dc analysis `dcOp': CPU = 1.17233 s, elapsed = 1.17517 s.
Time accumulated: CPU = 2.69232 s, elapsed = 2.07718 s.
Peak resident memory used = 180 Mbytes.
仿真的时候出现某些电压信号不达标的问题，需要处理吗？