在线咨询 切换到宽版
eetop公众号 创芯大讲堂 创芯人才网

 找回密码
 注册

手机号码,快捷登录

手机号码,快捷登录

搜帖子
查看: 1722|回复: 25

[资料] Circuit-Technology Co-Optimization of Sram Design in Advanced CMOS Nodes

[复制链接]
发表于 2025-2-4 12:11:44 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

×
Circuit-Technology Co-Optimization of Sram Design in Advanced CMOS Nodes
Modern computing engines--CPUs, GPUs, and NPUs--require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes.
The first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss.
In the second part, the focus shifts to a top-down DTCO approach due to the diminishing returns of bitcell scaling beyond 5 Å node at the macro level. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA. However, this approach can result in increased inter-subarray interconnect overhead, potentially offsetting macro-level improvements. This book examines the effects of various subarray sizes on macro-level PPA and finds that larger subarrays can significantly reduce interconnect overhead and improve the energy-delay-area product (EDAP) of SRAM macro. The introduction of the active interconnect (AIC) concept enables the use of larger subarray sizes, while integrating carbon nanotube FET as back-end-of-line compatible devices results in macro-level EDAP improvements of up to 65% when transitioning from standard subarrays to AIC divided subarrays. These findings highlight the future trajectory of SRAM subarray design in deeply scaled nodes.
(下載後, 後綴 *.001.7z 改成 *.7z.001)
Circuit-Technology Co-Optimization of Sram Design in Advanced CMOS Nodes.jpg


Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes, 2025_H.7z

30 MB, 下载次数: 159 , 下载积分: 资产 -9 信元, 下载支出 9 信元

Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes, 2025_H.7z

30 MB, 下载次数: 158 , 下载积分: 资产 -9 信元, 下载支出 9 信元

Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes, 2025_H.7z

21.73 MB, 下载次数: 147 , 下载积分: 资产 -7 信元, 下载支出 7 信元

发表于 2025-2-4 13:02:57 | 显示全部楼层
谢谢分享
发表于 2025-2-4 13:24:33 | 显示全部楼层
Good.
发表于 2025-2-4 13:52:39 | 显示全部楼层
多谢分享
发表于 2025-2-4 15:14:00 | 显示全部楼层
感谢分享   
发表于 2025-2-4 16:02:44 | 显示全部楼层
thanks
发表于 2025-2-4 16:30:02 | 显示全部楼层
谢谢分享
发表于 2025-2-4 18:54:41 | 显示全部楼层
can not un-compress ,

File corrupted ?


I use 7zip



发表于 2025-2-4 19:28:36 | 显示全部楼层
多谢分享。。
发表于 2025-2-4 20:30:56 | 显示全部楼层
xuexiyi=xia
您需要登录后才可以回帖 登录 | 注册

本版积分规则

手机版| 小黑屋| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-5-29 18:54 , Processed in 0.164628 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表