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[1]Yang, Dihang.A Multi-Loop Calibration-Free Phase-Locked Loop (PLL) for Wideband Clock Generation[D].ProQuest Dissertations and Theses Full-text Search Platform,2019.
[2]Abedi, Razieh.A 53-61GHz Low-Power PLL in 65nm CMOS[D].ProQuest Dissertations and Theses Full-text Search Platform,2017.
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