Bias Circuit Design For 1nA using UMC 180nm PDK

sennajar160 · 发表于 2018-1-31 21:47:35

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Hi, I have to Design 1nA bias circuit with Nmos and Pmos cascade transistors but in UMC 180nm pdk maximum length allowable is 50um.. how to design such low bias circuit please need your help..
Thanks in advance...

xiaowanzi88 · 发表于 2018-2-2 10:36:14

1nA, 异想天开~~~关断漏电通常都是0.1uA~1uA

sennajar160 · 发表于 2018-2-5 18:20:00

"An 1-V, 74-dB, sub-Hz Gm-C filter based on a modular transconductance reduction technique"

In This work authors designed OTA with tail current range from 0.1nA to 10nA...

How to design 1nA cascade bias circuit using UMC 180nm PDK...
thanks in advance..

ysliu168 · 发表于 2018-2-22 08:28:46

thanks for your sharing

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