how to change VHDL code to get rid of latch's

xiaoyisimonguo

please help, I need to change the following code to get rid of the latch synthesized
clk_en_latch: PROCESS(clk_enable, clk)
  BEGIN
    IF clk = '0' THEN
      latched_clk_en <= clk_enable;
    END IF;
  END PROCESS;



many thanks