NVIDIA英伟达职位：ASIC Physical Design engineer

NVHR

RESPONSIBILITIES:
Chip integration and netlist generation
Synthesis, Formal verification, netlist quality check
Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
Develop flow to physically partition and floorplan the entire chip.
Develop scripts for performing ECO's.


MINIMUM REQUIREMENTS:
BS or MS in Electrical Engineering or Computer Science
Above 2 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
Excellent scripts skills
Excellent written and verbal communication skills in English
Ability to multiplex many issues, set priorities, and work in a team environment
Keep up to date with leading edge technologies