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如上图所示,set_output_delay [expr 0.8-0.07]不是特别明白??
文件给出的解释是下面这段英文描述,还是请高人指点,JOE's design的flip-flop为什么capture time是2.3呢?
我觉得应该是2.37啊,2.37=2+0.3+0.07,所以我觉得outputdelay = 0.8 -(0.12-0.07)=0.8-0.05才对啊,求高人指点!!!
JOE’s_DESIGN has the same source latency as MY_DESIGN (0.30ns), but a different network
latency of 0.07ns (vs. 0.12ns in MY_DESIGN). To model this:
1) We “keep” the set_clock_latency –source 0.3 effect on MY_DESIGN’s output
ports by doing nothing with it
2) We remove the incorrect network latency affect of set_clock_latency 0.12 on
MY_DESIGN’s output ports by using set_output_delay …
-network_latency_included
3) We subtract the correct network latency from the output delay amount (expr 0.8 - 0.07)
to model the later required arrival time of the output data.
(Remember: A larger output delay value means that the data must arrive more time before the
capturing clock edge, or earlier; To model a later output data arrival time you must therefore
decrease the output delay amount. |
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