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用verilogams写了个模拟模块,输出电压是输入电压的平方以及开方关系,仿真遇到下面的错误
ncelab: *E,CUVDNF (./ihnl/test/tuning/schematic/verilog.vams,76|13): Could not determine discipline for this expression .
co ), .pin( net037 ) );
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ncelab: *E,CUVDNF (./ihnl/test/tuning/schematic/verilog.vams,77|17): Could not determine discipline for this expression .
net037 ), .ns( cds_globals.\gnd! ) );
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ncelab: *E,CUVDNF (./ihnl/test/tuning/schematic/verilog.vams,83|5): Could not determine discipline for this expression .
V0 ( ref, cds_globals.\gnd! );
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ncelab: *E,CUVDNF (./ihnl/test/tuning/schematic/verilog.vams,101|7): Could not determine discipline for this expression .
求解答!!! |
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