[PLL系列丛书之九]Phase-Locked Loop Circuit Design by Dan H. Wolaver

zhongkaiwang

不能解压……

hyz

有点小贵，并且诶不能解压，郁闷得很呀

mxh7408

太零碎了

yxy7968

能够解压，但希望以后这样的文档不用分开压，显得不够厚道。

sathya

A phase detector output of +1 makes the divide-by-M circuit count up. A phase
detector output of -1 makes the divide-by-M circuit count down. Therefore, the
output frequency from the divide-by-M counter has an average value described by
(9.72):
Df = uFM /M (9.72)
Equation (9.73) gives the gain of the VCO block by substituting (9.72) into (9.70)
and taking the derivative:
Kv = dfout /du = FM /(2MN) (9.73)
Figure 9.72 shows a block diagram using these constants. The l/s block converts
frequency to phase. Figure 9.72 models a first-order loop. Equation (9.74) computes
the unity-gain bandwidth from multiplying the blocks in the figure:
vx = K = [2FM /(MN)] rad/cycle

markhorrow

非常感谢提供！

nnltshan

谢谢分享，加油，努力

joannelin2214

感謝囉

zlysse

又是你，发的文档3个都无法解压，你干什么啊

qth1202

thanks