这个加法器什么意思？

sjdz2006

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity adder1 is
  port(a,b:in signed(7 downto 0);
      clk,en:in std_logic;

result: buffer signed(7 downto 0));
end adder1;

architecture dataflow of adder1 is
begin
   process(clk,en,a,b)
    begin
       if(clk'event and clk='1'and en='1')then

       result<=a+b;

  if(a(a'left)=b(b'left))and result(result'left)/=a(a'left) then

    result<=(result'left=>a(a'left),

             others=>not a(a'left));

   end if;

    end if;

end process;
end dataflow;

sjdz2006

如果a，b的左端都为1那么结果为100 0000  ？