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楼主 |
发表于 2013-9-9 17:23:51
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再贴个线性风格的Round-Robin基础仲裁部件(固定优先级)
module unit_arbiter(
clk,
rst_b,
en,
din,
dout
);
parameter DW = 4;
input wire clk;
input wire rst_b;
input wire en;
input wire [DW-1:0] din;
output reg [DW-1:0] dout;
//universal model for instance
always @(posedge clk or negedge rst_b)
if(!rst_b)
dout <= 4'd0;
else if(en) begin
if(din[0]==1'b1)
dout <= 4'd1;
else if(din[1:0]==2'd2)
dout <= 4'd2;
else if(din[2:0]==3'd4)
dout <= 4'd4;
else if(din[3:0]==4'd8)
dout <= 4'd8;
else
dout <= dout; end
//dout <= 4'd0; end
else
dout <= {DW{1'b0}};
endmodule |
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