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i have designed a bandgap (opamp+bjt), in pre-simulation, the DC/AC/TRAN are all ok; but in post-simulation, the output of bandgap is only a few mV lower than vdd, when vdd is 2.1V,it is 2V.it should have to be adjacent to 1.2V in pre-simulation; i checked the simulation result, i found that, the voltage difference between positive and negative end of opamp is about 100mV (so big difference, only 10uV for pre-simulation), i think maybe it is the reason.
later, i used non-parasitic post-layout netlist (NO RC or ONLY R, just like pre-simulation netlist), but i get the right result, so my layout have problems,but DRC and LVS have both passed,How can I correct my problem? or any other reasons? can anyone have met the same problem? or any advice?
Thank you in advance. |
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