这次上传的两个附件中的文章包括：
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy
A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms
A Low Power BAW Resonator Based 2.4-GHz Receiver With Bandwidth Tunable Channel Selection Filter at RF
A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer
Correction to “A 2 Gb／s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
The Outphasing RF Power Amplifier： A Comprehensive Analysis and a Class-B CMOS Realization
Correction to “A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing”
eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-5-27 21:36:29
创芯人才网