Questions related to STIL DFT protocol file[DFT&TetraMax]

web1987

I met a problem about writing a spf.
1. During the initial stage, the test clock pin is required to set at 1'b1 for serving as a control signal (like reset), and then become to 1'b0 after a period of 5000ns.
2. After the reset is done, the test mode can only be triggered by a sequence of control inputs. And then the clock can be pulsed to start the scanning.

I tried to use V { "clk" = 1} in "test_setup" section to force the clk is in high state during the beginning. But the tetramax complains errors that "clk" should be pulsed, not forced on.

How can I write such spf for tetramax?

Thx a lot.

yangxb303

顶顶更健康

pinpinse

怎么样了？是不是可以这样，定义一个1在clk的wft中，你可以试试