[ UMC ] 90nm PDK

linyis · 发表于 2014-11-27 21:24:12

支持楼主啦

naoz · 发表于 2014-11-27 22:18:41

这种侵权资料版主趁早删除啊！

RF007_2008 · 发表于 2014-11-28 17:34:13

太牛B了!NIUBILITY

ericsonpfc · 发表于 2014-11-29 15:11:35

今天網站怪怪的?

tuguoping1989 · 发表于 2014-12-8 11:21:22

还好，就是有点贵

nareshreddy · 发表于 2014-12-10 01:42:30

hhgfhgfhgfhgfhgfhgf

go2hell · 发表于 2014-12-24 10:19:23

好东西

Ryan67 · 发表于 2015-1-9 01:02:00

Hi,
  I'm new in Cadence and I'm designing circuits with TSMC0.13um PDK. My circuit contains 8 layers, but I don't know; how to place a via between two layers? for example metal via between met1 and met2.
  I'm trying to do this in schematic, may be this is not possible in the schematic? because in the vias folder of my KitDesign TSMC90nm there are only symbolic and layout folders? if this is correct in which step, we can add vias between layers and via_gnd to take their influence in the performance of the designed circuits (during simulation with cadence).
  I will appreciate your help

.

ic_shuo · 发表于 2015-1-11 11:06:00

谢谢分享

ic_shuo · 发表于 2015-1-11 11:31:11

有权限吗？为什么放不到虚拟机上啊

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