关于system generator的软硬件设计问题

stevenzhang81

大家好，我用到了system generartor(SG)里面的edk模块，SG和EDK之间通过shared memory进行通信。我首先建立一个EDK的xps工程，可以正常生成网表和bit文件。当我在SG里面导入这个xps工程后，由于加载了SG的shared memory模块，使xps的硬件结构发生了变化，然后我可以正常生成网表，但是生成bit文件的时候却不成功，提示一大堆让我费解的错误。不知道是否有人这么操作过，还请不吝赐教。

ERROR:MapLib:979 - LUT5 symbol
   "RS232_Uart_1/RS232_Uart_1/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_din_1_rstpot"
   (output
   signal=RS232_Uart_1/RS232_Uart_1/UARTLITE_CORE_I/UARTLITE_RX_I/fifo_din_1_rst
   pot) has input signal
   "RS232_Uart_1/RS232_Uart_1/UARTLITE_CORE_I/UARTLITE_RX_I/rx_2" which will be
   trimmed. See Section 5 of the Map Report File for details about why the input
   signal will become undriven.
ERROR:MapLib:979 - LUT3 symbol
   "RS232_Uart_1/RS232_Uart_1/UARTLITE_CORE_I/UARTLITE_RX_I/running_rx_2_AND_7_o

1" (output
   signal=RS232_Uart_1/RS232_Uart_1/UARTLITE_CORE_I/UARTLITE_RX_I/running_rx_2_A
   ND_7_o) has input signal
   "RS232_Uart_1/RS232_Uart_1/UARTLITE_CORE_I/UARTLITE_RX_I/previous_rx" which
   will be trimmed. See Section 5 of the Map Report File for details about why
   the input signal will become undriven.