这个论文中没有提到,关于这个结果的描述如下:a combination of transistors are turned on. By variation of
the digital input bits, the delay can be increased and decreased.
Fig.5 shows the delay for different input bit vectors. For
reasons of clarity not all bit combinations are shown. The
other delays lie between the presented lines. This concept
ensures a controlled delay of the rising and falling edge that
corresponds to a time delay of the whole signal, as needed for
the trimming of the comparator.
我认为这个蓝色的可能表示未进行调节时的曲线(就是没有上面的一排PMOS和下面的一排NMOS)
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发表于 2012-7-21 22:44:29
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