请问下这是什么错误？谢谢~~~

ineedpower

ERROR : Place:1063 - The delay controller "U_pp/top0/DATA_PATH_0/TAPLOGIC_0/IDELAYCTRL1" has been locked with the following location constraint: COMP "U_pp/top0/DATA_PATH_0/TAPLOGIC_0/IDELAYCTRL1" LOCATE = SITE "IDELAYCTRL_X2Y6" LEVEL 1 However, none of the delay elements calibrated by this controller are being used. The delay controller should be removed from the design and the net "U_pp/top0/DATA_PATH_0/TAPLOGIC_0/idelay_ctrl_rdy1" should be connected to GLOBAL_LOGIC_1. Please correct your design and rerun. 意思是说我虽然约束了IDELAYCTRL，但是在设计中却没有使用么？

abnerliu

It looks like you are using FPGA.

The message says your "delay" element is no use.
Tool suggests you to remove that element and rerun
again.