lexra 4189 MMU

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Memory Management Unit
The memory management unit (MMU) is an optional feature of the LX4189 processor. This
chapter discusses the implementation of the MMU.
A summary of the features is
• Implements the R2000/R3000 memory management system, with
some minor modifications
• Implements fixed 4Kbyte memory pages, with 32-bit virtual and
physical addresses and a 6-bit ASID.
• The 4GB address space is broken up into 2GB user space(kuseg),
0.5GB unmappable, cacheable kernel space (kseg0), 0.5GB
unmappable, uncacheable kernel space (kseg1), and just less than
1GB of mappable kernel space (kseg2). The remainder of kseg2 (16
MB) is dedicated to specific debug devices.
• The TLB is composed of a configurable number of entries.
Configuration options are: 4, 8, 16, 32, 64 entries
• Implements ENTRYHI, ENTRYLO, INDEX, RANDOM registers, based
on R2000/R3000 implementation. Implements a read-only WIRED
register, according to R4000 implementation.
• Signals the appropriate UTLB exception (TLBL or TLBS) or the
appropriate BEV0/BEV1 exception (TLBL, TLBS, MOD)
• Implements the TLBP, TLBR, TLBWI, TLBWR instructions

tbb2009

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