library ieee;
use ieee.std_logic_1164.all;
entity shift7 is port(
in0: in std_logic_vector(3 downto 0);
sel:in std_logic_vector(1 downto 0);
out0: out std_logic);
end shift7;
architecture archmux of shift7 is
begin
mux4_1:process(sel)
begin
case sel is
when "00" => out0 <= in0(0);
when "01" => out0 <= in0(1);
when "10" => out0 <= in0(2);
when "11" => out0 <= in0(3);
when others=>null;
end case;
end process mux4_1;
end archmux;