//------------------------------------------------------------------------------
// Address phase signals
//------------------------------------------------------------------------------
// The address decode is done in two stages. This is so that the address
// decode occurs in only one process, p_AddrOutPortComb, and then the select
// signal is factored in.
always @ (Addr or REMAP)
begin : p_AddrOutPortComb
case (Addr [31:28])
4'b0000 : begin
if (REMAP[1:0] == 2'b00)
// Bus-switch output 2, OTP
AddrOutPort = 4'b0010;
else if (REMAP[1:0] == 2'b01)
// Bus-switch output 1, OCRAM
AddrOutPort = 4'b0001;
else
// Bus-switch output 0, BOOTROM
AddrOutPort = 4'b0000;
end
4'b0001 : begin
if (REMAP[2])
// Bus-switch output 2, OTP
AddrOutPort = 4'b0010;
else
// Bus-switch output 0, BOOTROM
AddrOutPort = 4'b0000;
end
// Bus-switch output 1, OCRAM
4'b0110,
4'b1000 : AddrOutPort = 4'b0001;
// Bus-switch output 3, default slave
default : AddrOutPort = 4'b0011;
endcase // case(Addr [31:28])
end // block: p_AddrOutPortComb
// Select signal decode
always @ (Sel or AddrOutPort)
begin : p_SelComb
Sel0 = 1'b0 ;
Sel1 = 1'b0 ;
Sel2 = 1'b0 ;
Sel3 = 1'b0 ;
if (Sel)
begin
case (AddrOutPort)
4'b0000 : Sel0 = 1'b1 ;
4'b0001 : Sel1 = 1'b1 ;
4'b0010 : Sel2 = 1'b1 ;
4'b0011 : Sel3 = 1'b1 ;
default: begin
end
endcase // case(AddrOutPort)
end // if (Sel)
end // block: p_SelComb